Quantum Tunneling at 1 Nanometer: The Physical Boundary of Moore's Law

On October 6, 2016, researchers at the Lawrence Berkeley National Laboratory successfully activated a working transistor with a gate length of exactly one nanometer. That single experimental device, constructed not from standard silicon but from a combination of molybdenum disulfide and a metallic carbon nanotube, demonstrated that the physical boundaries of computation could be pushed further than classical physics suggested. The achievement established a clear dividing line in modern semiconductor engineering: the 1-nanometer wall is not the end of Moore's Law, but it is the absolute end of silicon as the foundation of global computing infrastructure.[5]

The argument for silicon's demise rests on a phenomenon called quantum tunneling. In a standard transistor, the gate acts as a switch, physically blocking or allowing the flow of electrons to represent the ones and zeros of binary code. As manufacturers shrink these gates to pack more computing power onto a single chip, the physical barrier holding the electrons back becomes thinner. According to theoretical models published in the International Journal of Physics and Applications, when a silicon gate drops below approximately 1.2 nanometers in thickness, the tunneling current increases exponentially, degrading the subthreshold swing beyond the required 60 millivolts per decade limit.[1]

This teleportation is not a manufacturing defect; it is a fundamental property of quantum mechanics. At the nanometer scale, an electron ceases to behave strictly as a solid particle and acts as a probability wave. If the physical barrier is thinner than the wavelength of the electron, there is a non-zero mathematical probability that the electron exists on the other side of the closed gate. When millions of electrons tunnel through a closed transistor, the switch fails to turn off, leaking current, generating massive amounts of heat, and destroying the binary logic required for computation.[1][2]

The semiconductor industry has spent decades delaying this inevitability. Microchip USA notes that the future of semiconductor miniaturization has relied on increasingly complex three-dimensional architectures, such as FinFET and Gate-All-Around designs, to maintain electrostatic control over the electron channel without thinning the gate past the quantum limit. However, these architectural workarounds are reaching their physical exhaustion point. The industry cannot engineer its way out of the fundamental laws of physics using silicon.[3]

The solution, as demonstrated by the Berkeley Lab team, requires abandoning the material that gave Silicon Valley its name. Transition metal dichalcogenides, specifically molybdenum disulfide (MoS2), offer a different atomic structure. Electrons flowing through MoS2 encounter higher effective mass, meaning their quantum probability waves are tighter and less likely to tunnel through a barrier. This allows engineers to scale the gate down to a single nanometer while still maintaining the ability to physically block the electron flow.[4][5]

Replacing the silicon channel is only half the equation; the gate itself must also be rebuilt. AIP Publishing research details the operation of these 1-nanometer devices using metallic carbon nanotubes as the gate electrode. A carbon nanotube, a hollow cylinder of carbon atoms exactly 1.0 nanometer in diameter, provides the precise electrostatic control required to switch the MoS2 channel on and off. This combination of a 2D material channel and a 1D nanotube gate represents the strongest current candidate for the next generation of ultra-scaled electronics.[4]

Further research is expanding the catalog of potential silicon replacements. Recent ab-initio quantum transport simulations published by ACS Publications have modeled the behavior of monolayer and bilayer tungsten diselenide (WSe2) transistors at sub-1-nanometer gate lengths. The simulations confirm that these ultra-scaled CMOS technologies can maintain high on-currents while suppressing quantum tunneling leakage, providing a theoretical roadmap for manufacturing chips that operate well below the silicon threshold.[6]

The transition to these new materials is not merely a theoretical exercise; it is an economic imperative for the global technology sector. The entire trajectory of artificial intelligence, advanced mobile computing, and data center efficiency relies on the continuous reduction of transistor size to increase processing density and reduce power consumption. If the industry hits a hard stop at the silicon tunneling limit, the exponential gains in computing power that have driven the global economy for fifty years will flatline.[2][3]

The challenge now shifts from theoretical physics to industrial manufacturing. Because these primary reference documents and laboratory announcements focus strictly on the mathematical and physical parameters of the devices, they do not contain conversational quotes from the researchers; however, the data itself speaks clearly to the physical limits. Growing uniform layers of MoS2 or WSe2 across a 300-millimeter wafer, and precisely aligning up to 50 billion carbon nanotubes without a single defect, requires entirely new fabrication facilities and techniques.[1][6]

The groundwork for this transition has been laid over more than a decade. As early as December 9, 2011, researchers at Penn State University were already documenting how quantum tunneling could be manipulated to achieve record transistor performance in experimental setups, using the phenomenon to their advantage in specialized tunnel field-effect transistors. That early research highlighted that quantum effects at the nanoscale are not just obstacles to be avoided, but properties that can be engineered.[7]

The 1-nanometer wall forces a strict reckoning between classical engineering techniques and the immutable laws of quantum physics. The compiled evidence across multiple research institutions confirms that while standard silicon has reached its physical terminus at the 1.2-nanometer mark, the broader field of computation has not. By actively embracing two-dimensional materials and carbon nanotubes, the global semiconductor industry is preparing to cross the quantum threshold. This material shift ensures that the relentless pace of miniaturization, which has defined the modern digital economy, will continue its trajectory deep into the sub-nanometer era.[2][4][5][8]