Intel Carves Out Advanced Packaging as Independent Division, Appointing Former SK Hynix CEO to Lead Effort
Intel has restructured its foundry business by establishing advanced packaging as a standalone division, tapping industry veteran Seok-Hee Lee to lead the effort. The move aims to break the global bottleneck in AI chip manufacturing and capture a larger share of the $55 billion packaging market.
By Factlen Editorial Team
- Industry Analysts
- Financial and market analysts view the restructuring as a highly lucrative pivot to capture a massive new market.
- Technology Press
- Hardware experts focus on the technical necessity of splitting front-end and back-end leadership.
- Global Supply Chain Observers
- International watchers emphasize the geopolitical stakes of moving chip assembly to the United States.
What's not represented
- · TSMC and Samsung executives facing new competition
- · Fabless startup founders seeking packaging capacity
Why this matters
Advanced packaging is the primary bottleneck preventing the tech industry from building enough AI chips. By dedicating an entire division and top-tier leadership to this problem, Intel is moving to unblock the global AI supply chain while bringing highly lucrative, cutting-edge manufacturing back to the United States.
Key points
- Intel has carved out its advanced packaging operations into an independent business division.
- Former SK Hynix CEO Seok-Hee Lee was appointed to lead the new unit.
- The move separates back-end packaging from front-end wafer fabrication leadership.
- Advanced packaging is currently the primary bottleneck in global AI hardware production.
- Intel aims to capture a significant share of the $55 billion packaging market by 2030.
- The restructuring coincided with a new domestic manufacturing partnership with Apple.
The artificial intelligence revolution is colliding with the physical limits of silicon. For decades, the semiconductor industry relied on shrinking transistors to boost computing power, a principle known as Moore’s Law. But as those microscopic switches approach the size of individual atoms, the traditional method of printing entire processors on a single, massive piece of silicon has become economically and physically unsustainable.
The solution lies not in making the chips smaller, but in how they are glued together. This discipline, known as advanced packaging, has quietly become the most critical bottleneck in the global technology supply chain. Every modern AI accelerator relies on complex architectural designs that stack logic processors directly alongside high-bandwidth memory.[3]
Recognizing this structural shift, Intel Corporation executed a decisive leadership overhaul on June 18, 2026. The company formally carved out its advanced packaging operations into an independent, hyper-focused business division within Intel Foundry.[1][2]
To lead this critical unit, Intel appointed Seok-Hee Lee as Executive Vice President. Lee brings a formidable resume to the role, having previously served as the Chief Executive Officer of South Korean memory giant SK Hynix and battery manufacturer SK On. He will report directly to Intel CEO Lip-Bu Tan.[1][2][4]

Lee’s mandate is sweeping. He will exclusively oversee advanced packaging, system integration, back-end technology development, and high-volume manufacturing operations. By elevating packaging to a standalone business with dedicated leadership, Intel is signaling that the back-end assembly of chips is now just as strategically vital as the front-end fabrication of the wafers themselves.[1]
This organizational split creates a clear division of labor. While Lee commands the back-end packaging, Naga Chandrasekaran, Executive Vice President of Intel Foundry, will narrow his focus entirely to front-end technology development, specifically accelerating the ramp-up of the company’s next-generation 18A and 14A manufacturing nodes.[4]
To understand why this restructuring matters, one must look at how modern chips are built. Instead of manufacturing a single, monolithic processor—where a single microscopic flaw can ruin the entire expensive chip—designers now use "chiplets." These are smaller, specialized components that are manufactured separately and then stitched together.
To understand why this restructuring matters, one must look at how modern chips are built.
The magic happens in the stitching. Intel is aggressively pushing two proprietary technologies into high-volume production: EMIB-T (an advanced version of the Embedded Multi-die Interconnect Bridge) and HBI (High-Density Hybrid Bonding).[4]

EMIB allows different chiplets to communicate at lightning speeds by embedding a tiny silicon bridge directly into the package substrate, avoiding the need for a large, expensive silicon interposer. Meanwhile, HBI enables true three-dimensional stacking. By bonding chips directly together using copper-to-copper connections, HBI drastically multiplies data bandwidth while slashing the power required to move that data.[4]
Currently, the broader semiconductor sector is constrained by the physical capacity limits of existing packaging lines. Taiwan Semiconductor Manufacturing Company (TSMC) operates the dominant advanced packaging platform, but surging order volumes from hyperscalers have left those facilities severely oversubscribed.[3]
This bottleneck has left major tech companies scrambling for alternatives. The massive total addressable market—projected to reach $55 billion by 2030—allows Intel to secure billions in new revenue simply by acting as a secondary supplier for tech giants desperate to avoid Asian supply chain constraints.[3]
The strategic pivot is already yielding dividends. On the same day as Lee’s appointment, the White House announced that Apple had agreed to partner with Intel to design and manufacture chips on American soil. This dual dose of positive news sent Intel’s stock surging by more than 10 percent, hitting an intraday all-time high and capping a massive 281 percent year-to-date rally.[1][3][4]

Beyond commercial demand, Intel possesses a unique structural advantage by operating as an integrated systems foundry within the United States. Operating domestic facilities allows the company to easily win lucrative defense contracts that strictly require secure North American supply chains—a hurdle its overseas competitors cannot clear.
Analysts view this independent packaging division as a masterstroke in Intel's broader IDM 2.0 turnaround strategy. Even if a fabless designer chooses to have its silicon wafers printed by TSMC or Samsung, Intel can still capture significant revenue by handling the complex back-end packaging of those chips.[3]
As the industry recognizes that back-end packaging is just as critical to computing performance as shrinking transistor sizes, Intel’s restructuring positions it at the exact center of the AI hardware boom. By dismantling the primary barriers to domestic silicon fabrication, the company is not just rebuilding its own foundry business—it is rewiring the global semiconductor supply chain.[3][4]
How we got here
April 2026
Intel lands Tesla as the first major customer for its next-generation 14A manufacturing process.
June 18, 2026
Intel officially appoints Seok-Hee Lee to lead the newly independent advanced packaging division.
June 18, 2026
The White House announces Apple's agreement to partner with Intel for domestic chip manufacturing.
Viewpoints in depth
Industry Analysts
Financial and market analysts view the restructuring as a highly lucrative pivot.
Analysts argue that the real bottleneck in the AI supercycle is no longer front-end wafer fabrication, but back-end packaging. By carving out this division, Intel can capture a massive share of the $55 billion total addressable market simply by acting as a secondary supplier to hyperscalers who are currently waitlisted at TSMC. They see this as the primary driver behind Intel's massive 281 percent year-to-date valuation expansion.
Technology Press
Hardware experts focus on the technical necessity of the split.
Technical observers note that managing front-end transistor scaling (like the 18A node) and back-end 3D stacking (like EMIB and HBI) require entirely different engineering disciplines. By splitting the leadership between Naga Chandrasekaran and Seok-Hee Lee, Intel is acknowledging that advanced packaging has graduated from a secondary assembly step to a foundational pillar of semiconductor architecture.
Global Supply Chain Observers
International watchers emphasize the geopolitical and competitive stakes.
Observers in Asia and global markets highlight the strategic poaching of Seok-Hee Lee from the South Korean ecosystem. They view Intel's move, coupled with Apple's commitment to domestic manufacturing, as a coordinated effort to dismantle the Asian monopoly on advanced chip assembly and secure sovereign supply chains for critical defense and AI infrastructure.
What we don't know
- Whether Intel can scale its HBI technology fast enough to meet hyperscaler demand in 2027.
- How TSMC will adjust its pricing and capacity expansion in response to Intel's aggressive move.
Key terms
- Advanced Packaging
- The process of combining multiple specialized semiconductor components into a single integrated system, rather than printing them on one large piece of silicon.
- Chiplet
- A small, specialized integrated circuit designed to be combined with others in a single package to form a larger, more complex processor.
- EMIB (Embedded Multi-die Interconnect Bridge)
- Intel's technology for connecting adjacent chiplets at high speeds by embedding a tiny silicon bridge directly into the package substrate.
- HBI (High-Density Hybrid Bonding)
- A 3D stacking technique that bonds chips directly together using copper-to-copper connections, drastically increasing data bandwidth and reducing power consumption.
- Front-End vs. Back-End
- Front-end refers to the creation of the microscopic transistors on a silicon wafer; back-end refers to cutting, packaging, and connecting those chips into a finished product.
Frequently asked
Why did Intel make advanced packaging a separate division?
To give it dedicated leadership and resources, recognizing that packaging—not just shrinking transistors—is now the primary bottleneck in AI hardware production.
Who is Seok-Hee Lee?
He is the former CEO of memory giant SK Hynix and battery maker SK On, recently hired by Intel to lead this new independent packaging division.
What is a chiplet?
A chiplet is a small, specialized component that is manufactured separately and then stitched together with other chiplets to form a larger, more powerful processor.
How does this affect the AI industry?
By expanding advanced packaging capacity, Intel aims to relieve the massive supply chain bottlenecks that have constrained the production of AI accelerators, offering an alternative to TSMC.
Sources
[1]ReutersGlobal Supply Chain Observers
Intel taps industry veteran Seok-Hee Lee to lead foundry packaging push
Read on Reuters →[2]Business KoreaGlobal Supply Chain Observers
Intel named the former SK Hynix chief to lead advanced packaging and backend technology
Read on Business Korea →[3]Investing.comIndustry Analysts
Silicon Supercycle: Constructing a Position in American Silicon
Read on Investing.com →[4]FutunnIndustry Analysts
Intel Foundry Scores Double Win: Poaches Former SK Hynix CEO to Lead Advanced Packaging
Read on Futunn →
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