TSMC Accelerates 2nm Chip Capacity Target to 120,000 Wafers Monthly on Surging AI Demand

Taiwan Semiconductor Manufacturing Co. (TSMC) is accelerating the rollout of its next-generation 2-nanometer silicon, targeting a production capacity of 120,000 wafers per month by the end of 2026. The revised timeline, reported Monday by Taiwanese industry publication EDN, pushes past earlier estimates of 90,000 to 100,000 wafers and represents a massive capital commitment to the physical limits of semiconductor manufacturing.[2][3][8]

The acceleration is a direct response to a 10% to 20% increase in advanced node orders from anchor clients, including Apple, Nvidia, AMD, Qualcomm, and MediaTek. To meet the revised target, TSMC is bringing five dedicated 2-nanometer fabrication plants online this year—two in Hsinchu and three in Kaohsiung.[3][4][5]

While "AI demand" is the marketing driver cited across the supply chain, the 120,000-wafer figure is an announced capacity target for late 2026, not current output. Today, the bulk of TSMC's leading-edge revenue still relies on its 3-nanometer and 5-nanometer nodes, heavily anchored by consumer electronics like Apple's iPhone processors, rather than purely enterprise AI accelerators. When asked about the aggressive new targets, TSMC declined to confirm the exact figures to local media, stating that "information related to capacity should be based on materials the company has officially released."[1][6]

Even so, the scale of the 2-nanometer ramp-up is unprecedented. According to TSMC senior vice president Hou Yung-ching, the first-year output of 2-nanometer wafers will be 45% higher than the initial yield of the 3-nanometer node in 2023. From 2026 to 2028, the company expects 2-nanometer capacity to grow at a compound annual rate of 70%.[3]

The 2-nanometer architecture, known internally as N2, marks TSMC's transition to Gate-All-Around Field-Effect Transistor (GAAFET) technology. This design allows the foundry to deliver up to a 15% performance increase at the same power level, or a 30% power reduction at the same speed, compared to the current 3-nanometer standard.[1]

That efficiency gain has triggered a rush among chip designers. TSMC confirmed that the N2 node has already seen four times the number of tape-outs—the final design phase before manufacturing begins—compared to its 3-nanometer predecessor at the same stage in its lifecycle.[1]

Meanwhile, TSMC is also stretching its existing 3-nanometer capacity to its physical limits. The company is pushing to expand 3-nanometer output to 180,000 wafers per month by the end of this year, and up to 210,000 by mid-2027. To achieve this, the foundry is converting some of its older 5-nanometer production lines to handle 3-nanometer fabrication, while adding facilities in Taiwan, Arizona, and Japan.[6]

The aggressive expansion cuts against a recent narrative of an AI spending slowdown. Just days ago, Asian chip stocks, including memory giants Samsung Electronics and SK Hynix, slid after reports that OpenAI had paused part of its infrastructure buildout. TSMC's revised 120,000-wafer target suggests that while some software buyers may be adjusting their timelines, the foundational hardware layer is still accelerating.[7][8]

Financing this dual expansion requires a staggering capital outlay. TSMC has raised its 2026 capital expenditure outlook to a range of $60 billion to $64 billion, allocating roughly 70% to 80% of that budget specifically to advanced process technologies.[6]

The success of the 120,000-wafer target will depend on whether the end-market demand for AI applications and premium smartphones justifies the premium pricing TSMC will charge for N2 silicon. The next verifiable checkpoint arrives when TSMC releases its fourth-quarter capital expenditure breakdown, which will reveal exactly how much of that $64 billion budget has been committed to equipping the Kaohsiung fabs.[1][6]