Intel Becomes First to Use ASML's High NA EUV for High-Volume Logic Chip Production

Intel has officially become the first semiconductor manufacturer to use ASML's High Numerical Aperture Extreme Ultraviolet (High NA EUV) lithography in high-volume production. The Dutch equipment giant confirmed the milestone, marking the end of the technology's purely experimental phase and its formal entry into commercial chipmaking.[1][2]

The next-generation patterning technology is being deployed at Intel's fabrication facility in Hillsboro, Oregon. It is currently being used on the company's advanced 18A process node to manufacture a subset of its Core Ultra Series 3 processors, codenamed Panther Lake.[1][3]

Moving High NA EUV from the laboratory to the factory floor represents a monumental leap for the semiconductor industry. Until now, the massive machines had been confined strictly to research and development environments due to their immense complexity and cost.[2][4]

To understand the breakthrough, it helps to look at the mechanics of extreme ultraviolet lithography. Standard EUV systems use light with a wavelength of 13.5 nanometers to etch microscopic transistor patterns onto silicon wafers, a process that revolutionized chipmaking over the last decade.[2]

The "NA" in High NA stands for numerical aperture, which measures how much light an optical system can collect and focus onto the silicon. Standard EUV machines utilize a lens system with a numerical aperture of 0.33, which is nearing its physical limits for shrinking transistors further.[2][6]

ASML's new TWINSCAN EXE systems increase that numerical aperture to 0.55. This wider optical angle allows chipmakers to print features 1.7 times smaller than previous generations, achieving 8-nanometer resolutions in a single exposure.[6]

Without High NA, manufacturers trying to build sub-2-nanometer chips would have to rely on "double patterning"—running the wafer through a standard EUV machine twice to create denser lines. Double patterning is slower, more expensive, and significantly increases the risk of microscopic defects.[1][6]

Intel is not printing the entire Panther Lake chip with the new technology. Instead, the company is applying a hybrid approach, using High NA EUV to pattern only the most complex, dense layers of the processor, while the remainder of the chip is manufactured using conventional lithography.[2][4]

Crucially, ASML and Intel confirmed that these specific 18A layers are "dual-qualified." This means the exact same layer can be exposed using either an older 0.33 NA machine or a new 0.55 NA scanner, with the resulting silicon wafers being completely interchangeable.[1][2]

The dual-qualification strategy is a massive de-risking move. It allows Intel to match the production yields of its existing fleet while slowly ramping up the new technology, ensuring that any hiccups with the High NA machines do not halt the entire Panther Lake assembly line.[2][6]

The financial stakes of this transition are staggering. The TWINSCAN EXE:5200B machines are the most complex manufacturing tools ever built by humanity. Each unit weighs roughly 165 tons and carries an estimated price tag of $400 million—more than double the cost of standard EUV systems.[3][4]

This exorbitant capital expenditure has split the semiconductor industry's heavyweights. TSMC, the world's dominant contract chipmaker, has publicly stated it has no plans to adopt High NA EUV in the near term, arguing that the technology is currently too expensive to justify the investment.[5]

TSMC is instead opting to squeeze more life out of its existing 0.33 NA EUV fleet for its upcoming nodes, betting that its mastery of double-patterning will keep its margins intact without requiring half-billion-dollar machine upgrades.[5]

For Intel, the calculus is entirely different. The American chipmaker is betting that mastering High NA EUV early will allow it to leapfrog TSMC's technological lead and reclaim its historical position as the undisputed king of semiconductor manufacturing.[4][5]

The timeline of Intel's integration has been aggressive. The company took delivery of the first-generation EXE:5000 machine in early 2024 for its Oregon R&D site, followed by the high-volume EXE:5200B model, which features a higher-power light source and faster wafer handling.[1][6]

By running High NA EUV on commercial Panther Lake chips today, Intel and ASML are gathering invaluable real-world data on system uptime, defect rates, and manufacturing implementation that competitors simply do not have.[1][3]

This early integration paves the way for Intel's upcoming process nodes, such as the 14A technology, which will rely much more heavily on High NA EUV to achieve unprecedented transistor density.[2][6]

The push for denser patterning is largely driven by the insatiable demand for artificial intelligence compute. Smaller, more tightly packed transistors translate directly into more powerful and energy-efficient AI accelerators and data center processors.[1][4]

ASML's success in getting High NA EUV into volume production also boosted its financial outlook. The Dutch company raised its gross margin forecast to between 54 and 56 percent, projecting up to 45 billion euros in full-year sales amid surging demand.[5]

While the dual-qualification proves the machines work, the true test will be whether Intel can scale this process profitably across millions of wafers. For now, however, the semiconductor industry has officially entered the High NA era, turning theoretical physics into commercial reality.[1][3]