The Mechanics of AI Memory: How a Shift in Chip Stacking Strategy Reshapes the Supply Chain

On July 6, 2026, Dutch financial media and South Korean tech outlet ZDNet reported that memory giants Samsung and SK Hynix are weighing a delay in adopting "hybrid bonding" for their next-generation High Bandwidth Memory (HBM) chips.[1][2]

This strategic pivot immediately rippled through the semiconductor supply chain, sending shares of BE Semiconductor Industries (BESI)—a Dutch company that holds a first-mover advantage in hybrid bonding tools—down 7.5%.[1]

To understand why a delay in a niche manufacturing technique can erase hundreds of millions of dollars in market value, one must look inside the engine of the artificial intelligence boom. AI processors rely on HBM to feed them massive amounts of data at lightning speed, making memory packaging a critical bottleneck for global tech infrastructure.[4]

HBM achieves this speed by stacking multiple DRAM memory dies on top of each other, much like floors in a skyscraper, with microscopic vertical wires called through-silicon vias running through them.[7]

Currently, these layers are connected using micro-bumps—tiny spheres of solder. Manufacturers use techniques like Thermal Compression bonding or SK Hynix's proprietary Mass Reflow Molded Underfill to melt these bumps and fuse the layers together.[3]

However, the AI industry is demanding ever-taller architectures. The upcoming HBM4 generation requires stacking 16 layers of memory. Under the strict physical height limits set by the JEDEC standards body—capped at 775 micrometers—fitting 16 layers using traditional solder bumps becomes a severe physics problem.[4][8]

Enter hybrid bonding. This cutting-edge technique eliminates the solder bumps entirely, connecting the copper pads of one chip directly to the copper pads of another.[1][7]

Hybrid bonding allows for interconnect pitches below 10 micrometers, significantly reducing the physical height of the stack while improving signal integrity and power efficiency.[4][7]

But the technology is notoriously difficult to master at scale. It requires perfectly flat surfaces, flawless chemical mechanical planarization, and a cleanroom environment devoid of even the smallest dust particles.[4]

While SK Hynix recently verified a 12-die stack using hybrid bonding in its research labs, achieving the yields necessary for profitable mass production remains a steep hurdle for the entire industry.[3]

The turning point came when JEDEC recently relaxed its height specifications, giving memory makers a crucial window of flexibility to stick with proven methods.[4]

Capitalizing on this relaxed standard, Samsung and SK Hynix are now prioritizing alternative thermal management technologies to extend the life of their existing bonding equipment.[5]

Samsung is reportedly testing a dedicated thermal component called the Heat Path Block, while SK Hynix is developing a similar solution dubbed ICE HBM.[2][5]

These components sit alongside the memory stack to rapidly dissipate heat, addressing one of the primary bottlenecks of 16-layer stacks without requiring an immediate, multi-billion-dollar transition to hybrid bonding machines.[5]

For equipment suppliers like BESI and its partner Applied Materials, the delay introduces near-term uncertainty, though analysts maintain that hybrid bonding remains the inevitable endgame for the subsequent HBM5 generation.[1][4]

Ultimately, this supply chain pivot highlights the pragmatic reality of semiconductor manufacturing. By innovating around thermal limits rather than forcing an unready technology into mass production, the industry is ensuring that the hardware powering the AI revolution continues to scale reliably.[4][5]