Samsung Delays High-NA EUV Adoption to 1nm Node, Will Use Standard EUV for 2nm and 1.4nm

There is a persistent assumption in the semiconductor industry that the race for smaller, faster chips is won simply by buying the newest, most expensive manufacturing tools the moment they become available. The narrative suggests that whichever foundry plugs in the latest machine first automatically secures the technological crown. In reality, bleeding-edge silicon is an exercise in brutal economics. The true winner is often the manufacturer who can make the math work, balancing the theoretical capabilities of a new tool against the staggering costs of deploying it.

That economic reality was laid bare this week in Suwon, South Korea. Speaking at the 2026 Next-Generation Lithography + Patterning Conference, Samsung Foundry confirmed a significant shift in its manufacturing roadmap. The company announced it will delay the full-scale commercial deployment of ASML's next-generation High-NA Extreme Ultraviolet lithography machines until it reaches the 1-nanometer node, which is slated for mass production around 2030.[1][4]

The announcement represents a calculated pivot from Samsung's earlier ambitions. The foundry had initially explored introducing High-NA EUV for its upcoming 2-nanometer and 1.4-nanometer processes. Instead, those nodes will now rely entirely on standard EUV technology. By pushing the adoption of the new machines to the end of the decade, Samsung is signaling that the supporting ecosystem for the technology is simply not ready for the rigors of high-volume commercial manufacturing.[2][4]

To understand why a foundry would willingly delay adopting the world's most advanced manufacturing tool, it helps to look at what the machine actually does. Lithography is the process of using light to print microscopic circuit patterns onto silicon wafers. For the past several years, the industry standard has been Extreme Ultraviolet lithography, which uses light with a wavelength of just 13.5 nanometers to draw features that are only a few dozen atoms wide.[4]

The new generation of these machines is known as High-NA EUV. The acronym stands for numerical aperture, a measure of the optical system's ability to gather and focus light. Standard EUV machines have a numerical aperture of 0.33. High-NA machines increase that aperture to 0.55. In optical terms, a wider aperture allows the machine to resolve even finer details, pushing the theoretical resolution limit down to 8 nanometers.[4][6]

The primary marketing promise of High-NA EUV is a concept called single patterning. When using standard machines to print the absolute smallest features on a 2nm chip, the circuits are too dense to be drawn in a single flash of light. Foundries must use multi-patterning, splitting the circuit design into two or more separate masks and exposing the wafer multiple times to build up the final pattern.[2][4]

Multi-patterning is notoriously difficult. It requires atomic-level alignment between the separate exposures, increases the risk of defects, and extends the time it takes to manufacture a wafer. High-NA EUV's superior resolution allows those same ultra-dense features to be printed in a single exposure, theoretically streamlining the manufacturing process and improving yields.[4][6]

However, the reality of deploying High-NA EUV is far more complicated than the marketing brochures suggest. The first hurdle is the sheer capital expenditure. A standard EUV machine is already one of the most complex devices ever built by humans, costing roughly $150 million to $200 million. A single High-NA EUV machine, by contrast, carries a price tag estimated between $350 million and $400 million.[2]

But the scanner itself is only one piece of the puzzle. The entire supply chain must be upgraded to support the new optics. High-NA machines use anamorphic lenses, which magnify the image differently in the horizontal and vertical axes. This halves the printable area on the wafer, meaning the machine has to print twice as fast to maintain the same throughput.[6]

Furthermore, the ecosystem of supporting materials remains immature. The industry is still struggling to perfect the specialized photoresists required for High-NA's unique optical properties. Crucially, the protective pellicles—ultra-thin membranes that shield the photomasks from microscopic dust—are not yet robust enough to handle the intense power of the High-NA light source in a high-volume setting.[2][3]

Park Chang-min, a Master at Samsung Electronics' Semiconductor Research Institute, made this exact point at the Suwon conference. He noted that while Samsung wanted to apply High-NA to the 2nm and 1.4nm nodes, the necessary technical improvements in the broader ecosystem simply have not materialized. The company concluded that forcing the technology into production too early would destroy the economic viability of the chips.[2][4]

Samsung's caution mirrors the strategy of its chief rival, TSMC. The Taiwanese foundry giant, which currently dominates the global market for contract chip manufacturing, has similarly stated that it does not plan to use High-NA EUV for mass production of its 1.4nm-class node. Like Samsung, TSMC is acquiring the machines primarily for research and development, holding off on commercial deployment until the economics make sense.[2]

The glaring outlier in this landscape is Intel. In a bid to regain its lost manufacturing crown, Intel has aggressively embraced High-NA EUV, becoming the first major foundry to deploy the technology for commercial production. Intel is currently using the $350 million machines to print select critical layers on its 18A and upcoming 14A process nodes. It is a high-stakes gamble: Intel is betting that an early learning curve will yield a long-term advantage, while Samsung and TSMC are betting that Intel is paying a massive premium to beta-test an unfinished ecosystem.[2]

With High-NA off the table for the immediate future, Samsung is adjusting its roadmap. The company will focus on refining its 2nm-class family of technologies over the next three years, ensuring high yields and stable volumes for major clients. To achieve the necessary density, Samsung will lean heavily on advanced multi-patterning techniques and Atomic Layer Etching using its existing fleet of standard EUV machines.[1][3]

Consequently, Samsung has pushed the timeline for its 1.4nm process from 2027 to 2029. This node will also rely on standard EUV. While multi-patterning at 1.4nm will be incredibly complex, Samsung has calculated that the known challenges of standard EUV are currently more manageable than the unknown variables of High-NA.[1][2][4]

The tipping point will finally arrive in 2030 with the introduction of Samsung's 1nm-class node. At this scale, the physical limits of standard EUV will be exhausted. The sheer number of multi-patterning steps required to draw 1nm features would make the process too slow, too prone to defects, and ultimately too expensive.[1][2][6]

Even then, the transition will not be absolute. When High-NA EUV does enter Samsung's production lines in 2030, it will coexist with standard EUV. Foundries will use a hybrid approach, reserving the expensive High-NA single-patterning exclusively for the most critical, ultra-dense layers of the chip, while using standard EUV for the rest.[3][6]

Ultimately, Samsung's delay is a sign of a maturing industry. The era of brute-force scaling—where foundries simply bought the newest tool to shrink the transistor—has given way to a delicate balancing act of physics, supply chain readiness, and commercial reality. By waiting for the ecosystem to catch up, Samsung is ensuring that the chips of 2030 will not only be technologically possible, but economically viable.