Imec and Ghent University Achieve 120-Layer 3D-Stacked DRAM Breakthrough for AI and Quantum Memory

The artificial intelligence industry is currently hurtling toward a physical brick wall. While processors and accelerators have grown exponentially faster, the memory chips required to feed them data are struggling to keep pace. Traditional Dynamic Random Access Memory (DRAM) is laid out flat on a two-dimensional plane, and engineers have nearly exhausted their ability to shrink those cells any further without causing severe electrical leakage. The proposed solution has long been to stop building outward and start building upward, mirroring the vertical stacking revolution that transformed NAND flash storage a decade ago.

However, stacking the crystalline structures required for high-speed DRAM is fundamentally different from stacking flash storage. It is less like stacking uniform sheets of paper and more like balancing a house of cards using materials that naturally want to warp and pull apart. Now, researchers at the Belgian semiconductor research hub imec and Ghent University have demonstrated a viable path forward. They successfully grew 120 alternating layers of silicon and silicon-germanium on a standard 300-millimeter production wafer, proving that extreme vertical scaling is physically possible.[1]

The core challenge the researchers had to overcome is known as lattice mismatch. Silicon and silicon-germanium crystals have slightly different atomic spacings. When stacked on top of each other, the layers naturally attempt to stretch or compress to match their neighbor. Without precise control, this accumulated stress causes the stack to warp, creating "misfit dislocations"—microscopic structural defects that ruin the electrical properties of the memory chip.[2]

To prevent the nanoscale skyscraper from collapsing under its own strain, the imec and Ghent University team had to act as atomic architects. They carefully tuned the germanium content in the alternating layers to exactly 20 percent. Furthermore, they experimented with introducing trace amounts of carbon into the structure, which acts as a subtle chemical glue to relieve the accumulated stress between the mismatched crystal lattices.[2]

The deposition process itself resembles painting with gases. Using advanced epitaxial techniques, the researchers introduced silane and germane gases into a reactor, where they broke down on the wafer's surface to leave behind precise, nanometer-thin layers. The resulting stack consists of approximately 65 nanometers of silicon paired with 10 nanometers of silicon-germanium, repeated 120 times to form the towering structure.[2]

Maintaining uniformity across a 300-millimeter wafer required extreme environmental control. The researchers noted that even minor hot or cold spots within the reactor's quartz tube could lead to uneven growth. By utilizing active temperature control systems, they managed to keep the interfaces between the layers remarkably sharp, limiting unwanted mixing and ensuring consistency from the bottom of the stack all the way to the 120th layer.[2]

It is important to distinguish this materials science breakthrough from a commercial product. This is not a finished 3D DRAM chip that can be slotted into a server tomorrow. Rather, it is the foundational substrate upon which those future memory cells will be carved. The next phase involves selectively etching channels through the silicon-germanium layers and building the actual capacitor and transistor structures—such as novel capacitor-less designs or Indium Gallium Zinc Oxide (IGZO) channels—within the vertical pillars.

Despite being an early-stage prototype, the implications are massive. Major memory manufacturers like Samsung have already placed 3D DRAM on their long-term roadmaps, anticipating that planar scaling will hit a hard limit before the end of the decade. Demonstrating that 120 defect-free bilayers can be grown on production-sized wafers de-risks the enormous capital investments required to retool fabrication plants for vertical memory architectures.[1]

The benefits of this extreme vertical scaling extend beyond traditional AI accelerators. The precise, atomic-level control over multi-layer structures demonstrated by the imec team is also highly relevant to the development of 3D transistors, stacked logic devices, and scalable quantum computing architectures. In quantum systems, controlling layer properties and minimizing defects at the atomic level is critical for maintaining qubit stability.[1]

While the industry celebrates the milestone, significant engineering hurdles remain. Researchers must still solve complex thermal management issues, as stacking heat-generating memory cells vertically makes cooling exponentially more difficult. Additionally, scaling the layer count even higher while maintaining yield and integrating the memory arrays with underlying logic circuits will require years of iterative refinement.

Nevertheless, the successful fabrication of the 120-layer stack marks a critical inflection point. It proves that the physics of 3D DRAM are sound, shifting the challenge from theoretical materials science to practical manufacturing and integration. As AI models continue to demand unprecedented memory bandwidth and capacity, breakthroughs like this ensure that the hardware foundation will be ready to support them.[1]