SK Hynix Engineers SSD Controllers Housing Over 100 Specialized Cores

On October 12, SK Hynix vice president Koo In-je stood before the International SoC Design Conference in Incheon and outlined a quiet crisis in storage hardware. General-purpose processors inside solid-state drive controllers, he argued, are finally hitting a wall in both power consumption and physical chip area.[5]

The problem stems from the relentless pace of data transfer standards. As PCIe bandwidth doubles with each new generation, the controllers managing that data flow have been forced to scale up their processing power just to keep up.[2][5]

Historically, manufacturers have solved this by packing more Arm-based central processing units into their controllers. Marvell’s PCIe 6.0 Bravera SC6, for example, utilizes 12 Cortex-R82 cores alongside several smaller security processors, a noticeable jump from its PCIe 5.0 predecessor.[2]

But SK Hynix contends that these conventional cores are fundamentally overpowered for the job. Arm CPUs are designed to execute complex, high-speed computations, making them an inefficient choice for the simple, highly repetitive tasks that make up the bulk of storage operations.[5]

"Currently, general-purpose CPUs inside SSD controllers are at their limits in terms of power consumption and area," Koo told the conference attendees.

Distributing the workload

To break the bottleneck, SK Hynix has engineered a custom, ultra-lightweight processor called the Hynix Transaction Processing Unit, or H-TPU. Rather than relying on a handful of powerful Arm cores, the company's new architecture distributes routine storage work across more than 100 of these specialized mini-cores.[1][5]

The H-TPU is not an artificial intelligence accelerator, despite the familiar acronym. It is a programmable processor built with a simple four-stage, in-order execution pipeline, specifically tailored to handle repetitive input and output data-transfer paths.[2]

By offloading the grunt work, the architecture frees up the controller's main CPU. The H-TPUs take over read and write command processing, metadata management, and buffer control, while the conventional processor is reserved for complex operations like error recovery and storage policy decisions.[5]

The efficiency claims presented in Incheon are striking. According to SK Hynix, a single H-TPU consumes approximately 2.5 percent of the power required by a standard general-purpose CPU core.[5][6]

The physical footprint is similarly reduced. The company states that each specialized core occupies just 4 percent of the die area of a conventional processor, allowing engineers to pack over a hundred of them into a single controller without inflating the silicon budget.[2][5]

Reading the fine print

However, these figures require careful reading. The power and area numbers represent a per-core architectural comparison against an unnamed baseline CPU, rather than a measurement taken from a finished, shipping solid-state drive.[1][6]

A controller housing more than 100 H-TPUs alongside a main Arm processor still has to be measured against a traditional multi-core Arm controller in real-world conditions. SK Hynix has not yet provided total package power consumption data or a single performance benchmark.[1]

The company also has not announced a specific controller model, a sampling date, or a commercial release timeline. The presentation at ISOCC 2026 was a disclosure of an architectural strategy, not a product launch.[1][6]

Furthermore, shifting to a highly specialized, proprietary architecture introduces software friction. SSD firmware teams have invested years in optimizing their Arm code, and adapting to a new ecosystem of over 100 parallel cores requires entirely new tooling.[1]

To address this, SK Hynix has developed a dedicated compiler and software suite to help engineers write specialized code for the H-TPU. The architecture also employs aggressive power gating, waking up only the specific cores needed for an incoming request while leaving the rest idle.[2]

A growing industry trend

While the scale of the H-TPU deployment is unusual, the underlying concept of domain-specific acceleration is already gaining traction across the storage industry. Competitors are actively exploring similar offloading strategies.[3][6]

Taiwan-based controller manufacturer Phison has utilized a CoXProcessor architecture in its enterprise products for some time. Its X1 controller pairs two Cortex-R5 cores with up to 32 dedicated micro-cores to handle repetitive firmware tasks at wire speed.[2]

SK Hynix is essentially taking that established approach and scaling it up to a much larger magnitude. The strategy reflects a broader shift in how the industry views memory, treating it less as passive storage and more as a heterogeneous system-on-chip.[2][3]

The H-TPU architecture is initially targeted at next-generation enterprise SSDs, where the unending chase for input/output operations per second makes the power bottleneck most evident. AI servers, which generate massive volumes of small, parallel storage requests, are a primary focus.[2][6]

The specialized cores are also slated for deployment in the company's upcoming High Bandwidth Flash, expected in 2027. That timeline signals that SK Hynix views the 100-core controller as the foundation for its future high-performance storage portfolio.[2]