TSMC Reportedly Begins Pilot Production of 1.4nm Chips Ahead of 2028 Target

Taiwan Semiconductor Manufacturing Company (TSMC) has initiated pilot production for its 1.4-nanometer chip manufacturing process, internally designated as A14. The trial runs are currently underway at two facilities in Taiwan, keeping the foundry on track for risk production in 2027 and high-volume mass production by 2028.[1][4][6]

Pilot production represents an early manufacturing stage used to test equipment, calibrate process steps, and measure initial yields before committing full production lines. It does not mean that 1.4nm chips are ready to ship in consumer devices or graphics cards. As noted in coverage by Softonic, the term "1.4nm" functions as a process generation name rather than the literal physical measurement of a transistor feature.[2][4]

The reported test manufacturing is taking place at the Hsinchu Science Park's Baoshan Fab 20 and the Central Taiwan Science Park's Fab 25. These two sites serve as the primary development hubs for TSMC's most advanced semiconductor nodes. By running test wafers now, TSMC allows its early customers—traditionally tech giants like Apple, Nvidia, and AMD—to evaluate how their future chip designs will behave in a physical production environment.[1][5]

The A14 node introduces specific, quantified performance targets over the upcoming 2-nanometer (N2) process, which is currently moving toward its own volume production. TSMC's official specifications project a 10% to 15% speed improvement at the same power level. Alternatively, chip designers can opt for a 25% to 30% reduction in power consumption when operating at identical speeds to the N2 node.[1][4][5]

To achieve these gains, the A14 architecture relies on second-generation nanosheet transistors and a NanoFlex Pro standard-cell design. Beyond raw speed and power efficiency, the 1.4nm process is expected to deliver a 20% increase in logic density. This density improvement allows engineers to pack significantly more computational power into the same physical die area, a critical metric for scaling artificial intelligence accelerators and high-performance computing hardware.[4][5]

To maintain this aggressive manufacturing timeline, TSMC is reportedly leveraging artificial intelligence and virtual reality in its fabrication plant development. According to TechPowerUp, AI systems handle image recognition and smart inspection on the factory floor. Simultaneously, VR simulations assist in training personnel for hazardous or high-altitude work, accelerating the overall readiness of the facilities.[5]

On the lithography equipment front, TSMC plans to continue utilizing Low-NA extreme ultraviolet (EUV) machinery for the A14 node. The company does not intend to transition to the more complex and expensive High-NA EUV tools until it reaches the 1-nanometer threshold. This represents a strategic divergence from rival Intel, which is aggressively adopting High-NA tools for its competing 14A process.[5]

The successful initiation of A14 pilot production helps solidify TSMC's roadmap through the end of the decade. Following the 1.4nm volume rollout in 2028, the company plans to introduce the A13 node in 2029. That subsequent process aims to shrink the overall die area by an additional 6% while maintaining design rule compatibility with A14, simplifying the transition for customers. None of the cited reports include direct statements or quotations from TSMC executives regarding the pilot phase, with the timeline details stemming from Taiwanese supply chain sources and the company's previously published roadmaps.[1][4][6]