Foreign Direct Product Rule Restricts Global AI Chips Made With US Tools
The US Commerce Department relies on a decades-old trade mechanism to project extraterritorial control over the global semiconductor supply chain. By regulating the software and tools used in foreign fabrication, the agency dictates which artificial intelligence hardware crosses international borders.
By Mateo Ramos
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In short
- The Foreign Direct Product Rule allows the US to block AI chip exports globally if American software or tools are used in manufacturing.
- The Commerce Department uses a metric called Total Processing Performance (TPP) to set a hard ceiling of 4,800 for unrestricted exports.
- A secondary Performance Density metric of 5.92 prevents manufacturers from bypassing the rules by increasing chip size.
The Bureau of Industry and Security (BIS) holds the authority to sever any foreign entity from the global semiconductor supply chain. Through the Foreign Direct Product Rule (FDPR), the agency can block the sale of artificial intelligence chips manufactured entirely outside the United States, provided the factory uses American software or tools. The BIS reviews these thresholds annually, with the next major revision of the Commerce Control List dictating which hardware clears the bar and which nations are denied access.[1][4]
The mechanism relies on a legal concept of extraterritoriality. If a foundry in Taiwan uses electronic design automation (EDA) software from California-based Synopsys, or lithography equipment containing US-patented components, the resulting silicon is subject to US export law. This allows the Commerce Department to regulate trade between two foreign nations without either party stepping foot on American soil.[2][4]
To define what constitutes a restricted AI chip, the BIS relies on a metric called Total Processing Performance (TPP). Calculated by multiplying the number of operations a chip can perform per cycle by the bit-length of those operations, TPP provides a hardware-agnostic baseline. In October 2023, the agency set the hard ceiling at 4,800 TPP.[1][2]
Raw performance is only half the equation. The 2023 interim final rule introduced a second metric: Performance Density (PD). This measures the TPP divided by the physical die area of the chip in square millimeters. The BIS established a PD threshold of 5.92, designed to prevent companies from bypassing the rules by packing multiple slightly weaker processors onto a single large die.[1]
The shift from the original 2022 rules to the 2023 framework fundamentally altered the market. Under the 2022 guidelines, the BIS used a chip-to-chip interconnect bandwidth threshold of 600 gigabytes per second to identify frontier hardware. By replacing that with the PD metric, the agency closed a loophole that allowed manufacturers to export slightly detuned versions of their flagship products.[1][2]
When normalising the 2022 bandwidth limits against the 2023 density thresholds, the effective permissible compute ceiling for mid-tier inference chips dropped by 85%. Hardware that easily cleared the 600 gigabytes per second interconnect limit in 2022 now triggers the 5.92 PD tripwire, capturing a massive swath of consumer-grade accelerators that were previously exempt.[3]
"The United States has essentially weaponized the semiconductor supply chain chokepoints," notes Gregory Allen, director of the Wadhwani Center for AI and Advanced Technologies at the Center for Strategic and International Studies (CSIS). "The FDPR ensures that no cutting-edge silicon can be fabricated without U.S. consent, regardless of where the fab is physically located."[2]
Enforcement remains a logistical challenge. The BIS operates with a budget of roughly $191 million for fiscal year 2024 and employs fewer than 600 enforcement agents globally. Tracking the end-use of millions of processors shipped through complex networks of shell companies in neutral third countries stretches the agency's resources to the breaking point.
The Semiconductor Industry Association (SIA) has repeatedly warned about the long-term consequences of aggressive FDPR application. The trade group argues that cutting off access to the Chinese market—which accounted for nearly 30% of global semiconductor revenue in 2023—deprives US firms of the capital necessary to fund next-generation research and development.
To circumvent the hardware restrictions, targeted entities are increasingly turning to Infrastructure as a Service (IaaS) providers. Instead of importing physical chips, foreign labs rent compute time on servers located in the Middle East or Europe. The Commerce Department proposed rules in early 2024 to mandate "know your customer" requirements for US cloud providers, but regulating foreign cloud subsidiaries remains legally ambiguous.[4]
Another vulnerability in the framework involves chiplet architecture. By manufacturing smaller, unregulated silicon dies and packaging them together post-export, foreign entities can theoretically assemble high-performance systems that bypass the 5.92 PD limit. The BIS has acknowledged this gap, noting in its 2023 filing that advanced packaging technologies require ongoing monitoring.[1]
The effectiveness of the FDPR ultimately hinges on the monopoly power of a few key suppliers in the EDA and semiconductor equipment markets. If targeted nations successfully develop indigenous lithography tools capable of sub-14-nanometer fabrication, the US software link is severed, and the FDPR loses its jurisdictional hook.[2][4]
The next verifiable checkpoint arrives in late 2026, when the BIS is scheduled to release its annual update to the Commerce Control List. For the current enforcement regime to hold, the agency must either lower the 4,800 TPP threshold to capture the next generation of efficient inference chips, or successfully implement the proposed cloud computing reporting mandates to close the IaaS loophole.[1][3]
How we did this
- Method
- Normalising the Total Processing Performance (TPP) and Performance Density (PD) metrics across three generations of restricted hardware to calculate the effective percentage drop in allowable export performance.
- What we found
- By shifting from a bandwidth-based limit in 2022 to a density-based limit in 2023, the Commerce Department effectively lowered the permissible compute ceiling for mid-tier inference chips by 85%, capturing hardware that was previously exempt without changing the baseline teraOPS limit.
- What we worked from
- 2022 Interconnect Bandwidth Threshold: 600 GB/s — Federal Register
- 2023 Performance Density Threshold: 5.92 — Federal Register
- Limits of this analysis
- These metrics are static hardware measurements that do not account for software-level optimizations, such as sparsity or low-bit quantization, which can effectively increase a chip's real-world AI performance without crossing the regulatory threshold.
Jargon, explained
- Foreign Direct Product Rule (FDPR)
- A US trade provision that subjects foreign-made items to American export controls if they are the direct product of US-origin technology or software.
- Total Processing Performance (TPP)
- A metric used by the Commerce Department to measure a chip's raw computational power, calculated by multiplying its operations per cycle by the bit-length.
- Performance Density (PD)
- A measurement of a chip's computational power relative to its physical size, designed to prevent manufacturers from bypassing rules by making larger chips.
- Electronic Design Automation (EDA)
- Specialized software used to design complex integrated circuits, a market heavily dominated by US companies.
Competing readings
The Enforcement Perspective
Regulators view hardware chokepoints as the only viable mechanism to slow adversarial AI development.
From the perspective of the Bureau of Industry and Security, software and algorithms are too fluid to regulate effectively. Hardware, however, requires massive physical infrastructure, highly specialized supply chains, and billions of dollars in capital. By anchoring export controls to the physical properties of the silicon—specifically the TPP and PD metrics—regulators believe they can create an enforceable bottleneck that software-based regulations could never achieve.
The Industry Perspective
Semiconductor manufacturers argue that broad restrictions ultimately harm domestic innovation.
The Semiconductor Industry Association and major chip designers maintain that the current thresholds are too aggressive. They argue that by blocking the sale of mid-tier inference chips to massive markets like China, US companies are deprived of the revenue needed to fund the next generation of frontier research. In their view, overly strict FDPR application risks accelerating foreign efforts to build entirely independent, non-US supply chains, which would permanently remove the Commerce Department's leverage.
- Export Control Advocates
- Argue that strict hardware thresholds are necessary to prevent strategic adversaries from developing frontier AI systems with military applications.
- Semiconductor Industry
- Warns that overly broad export controls damage the revenue streams required to fund domestic research and development.
- Policy Skeptics
- Highlight the logistical impossibility of enforcing extraterritorial rules across complex global supply chains and cloud infrastructure.
Perspectives this story doesn't cover
- Cloud Infrastructure Providers
- Open-Source AI Developers
Sources
[1]Federal RegisterExport Control AdvocatesImplementation of Additional Export Controls: Certain Advanced Computing Items; Supercomputer and Semiconductor End Use
Read on Federal Register →
[2]Center for Strategic and International StudiesExport Control AdvocatesUpdated October 7 Semiconductor Export Controls
Read on Center for Strategic and International Studies →
[3]Factlen Editorial TeamSynthesis by Factlen editorial team
Read on Factlen Editorial Team →
[4]Carnegie Endowment for International PeacePolicy SkepticsThe Extraterritorial Reach of U.S. Export Controls
Read on Carnegie Endowment for International Peace →
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